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Flexible implementation of genetic algorithms on FPGAs
http://hdl.handle.net/10061/11364
http://hdl.handle.net/10061/11364af33f9f8-4090-49cb-ab9f-80aa955cfb49
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
fulltext (168.1 kB)
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| Item type | 会議発表論文 / Conference Paper(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2017-01-10 | |||||
| タイトル | ||||||
| タイトル | Flexible implementation of genetic algorithms on FPGAs | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | genetic algorithm | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | FPGA | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | hardware design automation | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Knapsack Problem | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Traveling Salesman Problem | |||||
| 資源タイプ | ||||||
| 資源タイプ | conference paper | |||||
| アクセス権 | ||||||
| アクセス権 | open access | |||||
| 著者 |
Tachibana, Tatsuhiro
× Tachibana, Tatsuhiro× Murata, Yoshihiro× Shibata, Naoki× Yasumoto, Keiichi× Ito, Minoru |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Genetic algorithms (GAs) are useful since they can find near optimal solutions for combinatorial optimization problems quickly. Although there are many mobile/home applications of GAs such as navigation systems, QoS routing and video encoding systems, it was difficult to apply GAs to those applications due to low computational power of mobile/home appliances. In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture which consists of several modules for GA operations to compose a GA pipeline, and a parallel architecture consisting of multiple concurrent pipelines. The proposed architectures are simple enough to be implemented on FPGAs, applicable to various problems, and easy to estimate the size of the resulting circuit. We also propose a model for predicting the size of resulting circuit from given parameters consisting of the problem size, the number of concurrent pipelines and the number of candidate solutions for GA. Based on the proposed method, we have implemented a tool to facilitate GA circuit design and development. This tool allows designers to find appropriate parameter values so that the resulting circuit can be accommodated in the target FPGA device, and to automatically obtain RTL VHDL description. Through experiments using Knapsack Problem and TSP, we show that the FPGA circuits synthesized based on the proposed method run much faster and consume much lower power than software implementation on a PC and that our model can predict the size of the resulting circuit accurately enough. | |||||
| 書誌情報 |
p. 236-236, 発行日 2006 |
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| 会議情報 | ||||||
| 会議名 | FPGA '06 : ACM/SIGDA 14th international symposium on Field programmable gate arrays | |||||
| 開催期間 | Feb 22-24, 2006 | |||||
| 開催地 | Monterey CA | |||||
| 開催国 | USA | |||||
| 出版者 | ||||||
| 出版者 | ACM | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 1595932925 | |||||
| 出版者版DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1145/1117201.1117264 | |||||
| 権利 | ||||||
| 権利情報 | Copyright c 2006 ACM New York, NY, USA | |||||
| 著者版フラグ | ||||||
| 出版タイプ | AM | |||||
