{"created":"2023-07-25T10:26:27.980295+00:00","id":5055,"links":{},"metadata":{"_buckets":{"deposit":"ef1b5aaa-229f-4500-94d3-94eb8ba0feaf"},"_deposit":{"created_by":4,"id":"5055","owners":[4],"pid":{"revision_id":0,"type":"depid","value":"5055"},"status":"published"},"_oai":{"id":"oai:naist.repo.nii.ac.jp:00005055","sets":["34:36"]},"author_link":["13474","13475","144","215","13476"],"item_1698715929687":{"attribute_name":"会議情報","attribute_value_mlt":[{"subitem_conference_country":"USA","subitem_conference_date":{"subitem_conference_date_language":"en","subitem_conference_period":"Feb 22-24, 2006 "},"subitem_conference_names":[{"subitem_conference_name":"FPGA '06 : ACM/SIGDA 14th international symposium on Field programmable gate arrays ","subitem_conference_name_language":"en"}],"subitem_conference_places":[{"subitem_conference_place":"Monterey CA","subitem_conference_place_language":"en"}]}]},"item_9_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2006","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"236","bibliographicPageStart":"236"}]},"item_9_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Genetic algorithms (GAs) are useful since they can find near optimal solutions for combinatorial optimization problems quickly. Although there are many mobile/home applications of GAs such as navigation systems, QoS routing and video encoding systems, it was difficult to apply GAs to those applications due to low computational power of mobile/home appliances. In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture which consists of several modules for GA operations to compose a GA pipeline, and a parallel architecture consisting of multiple concurrent pipelines. The proposed architectures are simple enough to be implemented on FPGAs, applicable to various problems, and easy to estimate the size of the resulting circuit. We also propose a model for predicting the size of resulting circuit from given parameters consisting of the problem size, the number of concurrent pipelines and the number of candidate solutions for GA. Based on the proposed method, we have implemented a tool to facilitate GA circuit design and development. This tool allows designers to find appropriate parameter values so that the resulting circuit can be accommodated in the target FPGA device, and to automatically obtain RTL VHDL description. Through experiments using Knapsack Problem and TSP, we show that the FPGA circuits synthesized based on the proposed method run much faster and consume much lower power than software implementation on a PC and that our model can predict the size of the resulting circuit accurately enough.","subitem_description_type":"Abstract"}]},"item_9_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"ACM","subitem_publisher_language":"en"}]},"item_9_relation_11":{"attribute_name":"ISBN","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"1595932925","subitem_relation_type_select":"ISBN"}}]},"item_9_relation_13":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1145/1117201.1117264","subitem_relation_type_select":"DOI"}}]},"item_9_rights_14":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright c 2006 ACM New York, NY, USA","subitem_rights_language":"en"}]},"item_9_version_type_16":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tachibana, Tatsuhiro","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"13474","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Murata, Yoshihiro","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"13475","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Shibata, Naoki","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"144","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"40335477","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=40335477"}]},{"creatorNames":[{"creatorName":"Yasumoto, Keiichi","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"215","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"40273396","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=40273396"}]},{"creatorNames":[{"creatorName":"Ito, Minoru","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"13476","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2023-03-02"}],"displaytype":"detail","filename":"Flexible Implementation.pdf","filesize":[{"value":"168.1 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"fulltext","objectType":"fulltext","url":"https://naist.repo.nii.ac.jp/record/5055/files/Flexible Implementation.pdf"},"version_id":"9e4aba80-fa1e-485d-9060-6a74e35dc3e8"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"genetic algorithm","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"FPGA","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"hardware design automation","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Knapsack Problem","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Traveling Salesman Problem","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"conference paper","resourceuri":"http://purl.org/coar/resource_type/c_5794"}]},"item_title":"Flexible implementation of genetic algorithms on FPGAs","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Flexible implementation of genetic algorithms on FPGAs","subitem_title_language":"en"}]},"item_type_id":"9","owner":"4","path":["36"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2017-01-10"},"publish_date":"2017-01-10","publish_status":"0","recid":"5055","relation_version_is_last":true,"title":["Flexible implementation of genetic algorithms on FPGAs"],"weko_creator_id":"4","weko_shared_id":-1},"updated":"2023-11-08T09:35:05.202061+00:00"}